Welcome to Loïc Cudennec Website

  • Kalray MPPA-256 Many-core Processor
  • Intel Itanium Processor
  • Tera 100 / TGCC / Curie
  • Smart Manufacturing
  • Adapteva Parallella 64 Many-core Processor
  • Christmann RECS 3 Micro-server

In Short

Research Engineer at CEA, LIST in High-Performance and Embedded Computing.

I received both Engineering Degree and Master Thesis in 2005 at INSA de Rennes and defended my Ph.D. Thesis at the University of Rennes 1, co-funded by the INRIA Centre Bretagne Atlantique, Sun Microsystems and the Regional council of Brittany under the supervision of Luc Bougé and Gabriel Antoniu in the PARIS/KerData team.

Current works are related to heterogeneous computing and the data management over mixed shared and distributed memory architectures in massively parallel systems, in search of a tradeoff between performance and energy consumption. This includes many-core processors, micro-servers and computing grid architectures. Some projects I am/was involved in: H2020 M2DC (micro-servers), H2020 Exanode (Parallel processor for exascale computing), EIT Digital HII CPS (Industrie 4.0), Kalray joint laboratory (256-core processor), Grid'5000 (Computing grid).

With Stephane Louise (CEA), we organize the Alchemy Workshop, held in conjunction with the ICCS Conference, to present recent works on heterogeneous computing architectures.