Welcome to Loïc Cudennec Website

  • Kalray MPPA-256 Many-core Processor
  • Intel Itanium Processor
  • Tera 100 / TGCC / Curie
  • Smart Manufacturing
  • Adapteva Parallella 64 Many-core Processor
  • Christmann RECS 3 Micro-server

Short Biography

2009-today Research Engineer at CEA, Saclay.

Researcher in High-Performance and Embedded Computing.
2015-today In charge of CEA LIST partnership in M2DC and Exanode H2020 European projects on micro-servers and parallel chips.
2013-today Organization of the ICCS/Alchemy track on many-core processors.
2009-2012 CEA-Kalray joint laboratory: Design and implementation of several steps of the Sigma-C dataflow compilation toolchain for many-core processors.

2005-2008 Ph.D. Candidate at University of Rennes 1, INRIA, Rennes.

Research in Grid Computing and High Performance Computing.
5-month visit at Sun Microsystems, Santa Clara, USA : Performance evaluation of the JXTA peer-to-peer protocol.
Eligibility Qualifications for Assistant Professor in Computer Science (CNU Section 27) 2010 & 2015.

2003-2005 Master Engineering & Master Research in Computer Science at INSA Rennes.

5-month internship at INRIA: Research on data consistency models and protocols for grid architectures.
3-month internship at Siradel: Design and implementation of a data exchange format for the Volcano radio propagation model suite.

2001-2003 Bachelor's Degree in Computer Science at the University of Rennes 1.

3-month internship at EDF: Design and setting of the heavy-industry energy client database.
3-month internship at DGA: Design of an intranet application that manages authorizations for site access.